Microprocessors are defined in a single chip of semiconductor material as is well known in the art. A microprocessor includes a data path in which processing is carried out and a control section to generate the microcode which controls the various elements of the data path. The control section often includes one or more programmed logic arrays (PLA's) which respond to sequences of input commands (opcodes) to generate the outputs or microcode.
A PLA includes a decoder portion and a read only memory (ROM) portion. Input and output registers are connected to the decoder and to the ROM portions, respectively. A PLA usually also contains a feedback path between the output register and the input register. A PLA thus is responsive not only to opcodes but also to bits, in the feedback loop, which define the present state of the PLA and determine the next consecutive state in cooperation with a next consecutive opcode. In this manner, a finite state machine is realized.
A PLA includes a separate implementation (line of microcode) for each command (input) in its repertoire. Specifically, each distinct set or subset of inputs, to which a PLA is capable of responding, requires a separate path in the decoder and ROM portions. The resultant set of outputs, in any particular case, may be distinct or the same as those for one or more other sets of inputs.
Frequently, sequences of outputs are needed in response to more than one set of inputs as, for example, in an instruction fetch operation. In prior art PLA's, the sequences of outputs have to be implemented in each path for each distinct set or subset of inputs. The problem is that such redundant implementation of these sequences is wasteful of chip area.